As memory arrays have become faster and smaller, the trend has been to place such high-speed arrays entirely on-chip. Consider, for instance, computer systems. Until quite recently, memory, an integral part of any computer system, has been located on integrated circuit (IC) devices separate from the central processing unit (CPU) of the computer system. Communication between the CPU and separate memory devices was accomplished by porting the inputs and outputs of the memory arrays to package pins of the memory devices to the CPU via address and data busses. As IC fabrication technology has evolved to the sub-micron level, as evidenced by devices fabricated using a 0.25-micron or even smaller fabrication process, it has become possible to place large memory arrays, such as random access memories (RAMs), static random access memories (SRAMs), and cache RAMs, entirely on-chip with other circuitry, such as a CPU. On-chip memory arrays provide the advantage of direct communication with the CPU without the need for I/Os to external pins.
In spite of the advantages provided by placing memory arrays on-chip, there are concerns with how to accomplish testing of such on-chip arrays. On-chip memory arrays, which may account for a large portion, even a majority, of the total die area of a chip, are much harder to control and observe than their discrete predecessors, making it difficult to use traditional external tester equipment and hardware to test, screen, characterize, and monitor on-chip arrays. Visibility into how on-chip memory arrays function is severely limited by the placement of the array-chip interface, such as the interface between a memory array and a CPU core of a microprocessor chip, for instance, on-chip.
Often Built-In-Self-Test (BIST) methodology is used to test on-chip memory arrays. BIST offers the advantage of being on-chip with the memory arrays, thus allowing much greater visibility into memory array functionality than other testing methodologies located external to the chip. Referring to FIG. 1, a BIST implementation 10 is illustrated. BIST moves the test vector generation on-chip microprocessor 20 inside BIST block 24. Multiplexer 28, BIST block 24 and associated address and data bus 34 represent special BIST hardware in the memory datapath. Previous BIST solutions predominantly hard-wired the test vector generation within BIST block 24 to render only limited, fixed test functionality. In order to provide independent access to just the memory array(s) 22, as opposed to accessing the entire chip 20, BIST operation and extraction of test results are typically accomplished through IEEE Standard 1149.1 Joint Test Action Group (JTAG) boundary scan Test Access Port (TAP).
Sequencing through addresses is a fundamental part of testing most memory arrays. In order to properly test integrated circuit memory array devices, it is therefore necessary to generate addresses of the memory array to be tested. Memory arrays are arranged by rows and columns as shown in FIG. 2. An address into a memory array is divided into bits that access the columns of the array and bits that access the rows of an array. The address of each memory cell within the memory array is therefore determined by bits that access the column in which the memory cell is located and bits that access the row in which the memory cell is located.
A memory array composed of eight rows and eight columns, for a total of 64 memory cells, is shown in FIG. 2. Some examples of the address associated with various cells are shown in the figure. The Address A0 of the first cell is 000 000, with the least significant bits identifying the column of the cell and the most significant bits identifying the row of the cell. This particular ordering of the bits of the address is arbitrary and just for purposes of this example; it is understood that any desired ordering of the row and column bits of an address may be implemented. The Address A7 of cell 8 is 000 111. The Address A8, in the next row up and in the same column as the first cell, is 001 000; the column carry-out when moving from address A7 to address A8 is demonstrated in the incrementation of one of the row bits of the address.
Counters are commonly used to generate the addresses of the memory cells that are required for memory array testing and in BIST environments are characteristically the dominant means for generating these required addresses. Traditional counters, however, only increment or decrement in one fixed pattern, i.e. 0, 1, 2, 3, . . . or 10, 9, 8, 7, . . . , and in this lock-step approach, are useful for ensuring that every memory cell of the memory array is eventually accessed.
An important problem with this approach is that at-speed proximity testing of cells of the memory array is not possible. The long set-up procedures that are required before each access of the memory does not allow for at-speed testing of targeted memory cells. Additionally, eventual access of every cell is an oversimplified approach to testing large memory arrays that does not satisfactorily provide the means for effectively testing different kinds of memory cell defects in a targeted manner. For instance, the defects of a particular memory cell of the memory array, whether caused by manufacturing, electrical, or other problems, can be brought out by the transitions that occur in near-by or adjacent memory cells. Simply stepping through the memory may not detect the defect. A better approach is to access potential defective cells or cells of interest, and their neighboring cells. Current counter methods for generating addresses are not capable of such flexibility, however.
As an example, consider the defective memory array "x" shown in FIG. 3. "x" is surrounded by eight adjacent cells 1, 2, 3, 4, 5, 6, 7, and 8. For purposes of clarity, directions corresponding to north, south, east, and west are illustrated in FIG. 3. A traditional counter is only capable of generating addresses that correspond to either an upward or a downward movement. If the counter counted from a south (S) to a north (N) direction, for instance, it would first generate addresses corresponding to cell locations 6, 7, 8 so that these cells could be set by writing to them and then generate addresses corresponding to cell locations 1, 2, 3 so that these cells could be set. After memory cells 6, 7, 8 and then 1, 2, 3 have thus been changed, the "x" cell of interest would then be read to determine if its value has changed. If the "x" cell has changed, this indicates that "x" is defective.
Moving from S to N in this manner is not a complete test, however, for at least two reasons. First, this test did not set adjacent memory cells 4 and 5. The S to N movement only writes the rows around "x" and not the row that actually contains "x". Second, moving in a south to north direction ignores the three other possible directions of movement: north to south, east to west, and west to east. Memory cell "x" may be sensitive to the order in which the adjacent memory cells are written with respect to each other and writing the adjacent memory cells in only the S to N direction does not test this sensitivity. Even a counter that is capable of both incrementing and decrementing, corresponding to the S to N and N to S directions, for example, will only cover two of the four possible directions. Therefore, in order to have a complete and meaningful test of memory cell "x", it is necessary to approach "x" from all directions. No prior art counter is able to generate addresses that will provide memory cell testing from all four directions. What is lacking in the prior art, therefore, is the ability to generate addresses of the cells of a memory array in a manner that provides for complete and flexible testing of any desired cell or cells of the memory array.